SAR ADC and method thereof

摘要

A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.

主权项

1. A successive approximation register analog to digital converter, for generating a digital code in response to a differential analog input signal, comprising:
a comparator, having a first input terminal and a second input terminal; an input switch unit, arranged to couple the differential analog input signal to the comparator during a sampling phase and decouple the differential analog input signal to the comparator during a conversion phase; a positive conversion capacitor array, comprising a plurality of first positive capacitors and a plurality of first positive switches, arranged to sample a positive end of the differential analog input signal during the sampling phase, wherein each first positive capacitor is coupled between the first input terminal of the comparator and a corresponding first positive switch, respectively, for selectively coupling the first positive capacitor to either a first reference voltage or a common voltage; a negative conversion capacitor array, comprising a plurality of first negative capacitors and a plurality of first negative switches, arranged to sample a negative end of the differential analog input signal during the sampling phase, wherein each first negative capacitor is coupled between the second input terminal of the comparator and a corresponding first negative switch, respectively, for selectively coupling the first negative capacitor to either the first reference voltage or the common voltage; and a successive approximation register (SAR) controller, arranged to reset the first positive switches and the first negative switches at the end of the sampling phase to change an input voltage difference between the first and second input terminals of the comparator into a residual signal, generate an intermediate digital code to control the first positive switches and the first negative switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generate the digital code according to the intermediate digital code, and use an inverted intermediate digital code to control the first positive switches and the first negative switches at the end of the conversion phase.