Methodology to avoid gate stress for low voltage devices in FDSOI technology

摘要

An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

主权项

1. A device comprising:
a first semiconductor substrate; a dielectric layer on the first semiconductor substrate; a second semiconductor substrate on the dielectric layer and separated from the first semiconductor substrate by the dielectric layer; a gate dielectric layer on the second semiconductor substrate; a plurality of transistors each respectively including:
a gate terminal on the gate dielectric layer and separated from the second semiconductor substrate by the gate dielectric layer;a channel region in the second semiconductor substrate below the gate terminal; anda source and drain region in the second semiconductor substrate, the source and the gate terminal being electrically connected; a voltage source coupled to the first semiconductor substrate and configured to turn the plurality of transistors on or off by applying a high voltage or a low voltage to the first semiconductor substrate.