SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

摘要

A method of manufacturing a semiconductor memory device according to an embodiment comprises: stacking a first insulating layer on a semiconductor layer, the first insulating layer being provided with a first region, a second region, and a third region that are adjacent in a first direction; stacking a charge accumulation layer formation layer; stacking a second insulating layer; and stacking a first conductive layer. The method comprises: in the second region on the semiconductor layer, removing the first insulating layer, the charge accumulation layer formation layer, the second insulating layer, and the first conductive layer to expose the semiconductor layer. Moreover, the method comprises: stacking in the second region a third insulating layer; and stacking a second conductive layer. Furthermore, the method comprises: exposing an upper surface of the semiconductor layer in the third region.

主权项

1. A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising:
a NAND string provided in a first region on a semiconductor layer extending in a first direction, the NAND string including a plurality of memory cells connected in series; and a select gate transistor connected to an end of the NAND string in a second region on the semiconductor layer, the second region being adjacent to the first region from the first direction, the method comprising: stacking on the semiconductor layer a first insulating layer which will be a gate insulating layer of the memory cell; stacking on the first insulating layer a charge accumulation layer formation layer which will be a charge accumulation layer of the memory cell; stacking on the charge accumulation layer formation layer a second insulating layer which will be an inter-gate insulating layer of the memory cell; stacking on the second insulating layer a first conductive layer which will be a control gate electrode of the memory cell; in the second region, removing the first insulating layer, the charge accumulation layer formation layer, the second insulating layer, and the first conductive layer to expose the semiconductor layer; stacking in the second region a third insulating layer which will be a gate insulating layer of the select gate transistor; and forming on the third insulating layer a second conductive layer which will be a gate electrode of the select gate transistor.