Semiconductor device and method of manufacturing semiconductor device

摘要

A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

主权项

1. A method of manufacturing a semiconductor device comprising the steps of:
(a) forming a second well region of a second conductivity type including a fourth part on a semiconductor substrate; (b) on the semiconductor substrate, forming a first well region of a first conductivity type including a first part and a second part arranged to be adjacent to both sides of the fourth part in a first direction and a third part joined to the first part and the second part in a second direction intersecting with the first direction and arranged to be adjacent to the fourth part; (c) forming a first insulating film at a place on the first well region and the second well region except for a first source/drain pattern to be a partial region of the fourth part, a second source/drain pattern to be a partial region of the first part or the second part, and a power feeding pattern to be a partial region of the third part having a substantially-rectangular shape whose size in the first direction is larger than a size thereof in the second direction; (d) forming a gate layer having a linear shape and extending in the first direction so as to cross above the first source/drain pattern and above the second source/drain pattern; (e) partially etching the gate layer through mask process; and (f) introducing an impurity of the first conductivity type to the first source/drain pattern, introducing an impurity of the second conductivity type to the second source/drain pattern, and introducing an impurity of the first conductivity type to the power feeding pattern.