| 摘要 |
PROBLEM TO BE SOLVED: To shorten access time with instruction fetch to a main memory in condition branching instruction execution time without providing a complicated branch predicting mechanism in a CPU. SOLUTION: This device has a CPU 12 which incorporates the branch predicting mechanism for shortening time for access to a main memory 18 when a cache error occurs because of a condition branching instruction, a cache memory 10 to be the execution object of instruction fetch due to the CPU 12 at ordinary time, a branch establishment prefetch queue 14 to be the execution object of instruction fetch due to the CPU 12 when branch is established, a branch non-establishment prefetch queue 16 to be the execution object of instruction fetch due to the CPU 12 when branch is not established, a predecoder 22 provided outside the CPU 12 for judging the branching instruction and a memory controller 20 having an address generating function for memory access.
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