Oversampling clock recovery circuit applicable not only to high rate data but also to low rate data

摘要

In an oversampling clock recovery circuit comprising first through fourth phase comparators (PD1 to PD4) and a majority circuit (10), DOWN signal output terminals (DN2(out), DN3(out)) of the second and the third phase comparotors are connected to UP signal input terminals (UP3(in), UP4(in)) of the majority circuit and UP signal output terminals (UP3(out), UP4(out)) of the third and the fourth phase comparotors are connected to DONW signal input terminals (DN2(in), DN3(in)) of the majority circuit. <IMAGE>