Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide

摘要

A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

主权项

1. A method of forming a semiconductor structure, comprising:
forming an N+ doped silicon layer on a semiconductor substrate; forming an undoped SiGe layer on the N+ doped silicon layer; forming a silicon channel layer on the undoped SiGe layer; forming a plurality of fins by performing a fin etch on the semiconductor structure; depositing an oxide layer on the semiconductor structure and in between each of the plurality of fins; forming a thermally formed oxide region by performing an anneal on the semiconductor structure; forming a gate on the semiconductor substrate; performing an anisotropic etch into the semiconductor structure adjacent to the gate, and extending into the N+ doped silicon layer; and forming P+ doped SiGe regions adjacent to the gate and thermally formed oxide region, and extending into the N+ doped silicon layer.