DRAM CELL LAYOUT FOR NODE CAPACITANCE ENHANCEMENT

摘要

A layout pattern for increasing the spacing between the deep trenches (79, 81) of one cell pair and the deep trenches of an adjacent cell pair in an array of semiconductor DRAM cell pairs each of which cell pairs share a common bitline contact (77) to bitlines (87, 89, 91) arranged in one direction and each of which cell pairs are coupled to gate conductors (83) arranged orthogonal to the bitlines. The layout pattern is formed by positioning the deep trenches of all of said pairs along alternate bitlines so they are offset from said bitlines along gate conductors in opposing directions. The deep trenches of all of the remaining bitlines are offset from said bitlines in opposing directions opposite to the opposing directions of said trenches along said alternate bitlines so as to form a herringbone pattern of cells.