DETRIMENTAL LATCH-UP AVOIDANCE

摘要

The present invention relates to methods and arrangement to prevent detrimental latch-up in gates located in two independently powered supply domains. The gates are mutually connected via a bi-directional interface between the domains, and a voltage surveillance circuit is associated with the domains. The method comprises the following steps: detecting in the surveillance circuit, an improper supply of power to at least one domain of the two domains; generating an inhibit signal in the surveillance circuit; preventing logic high levels for signals on the bi-directional interface between gates located in the two domains.