PREPARING INSTRUCTION GROUPS IN A PROCESSOR HAVING MULTIPLE ISSUE PORTS

摘要

During program code conversion, such as in a dynamic binary translator, automatic code generation provides target code (21) executable by a target processor (13). Multiple instruction ports (610) disperse a group of instructions to functional units (620) of the processor (13). Disclosed is a mechanism of preparing an instruction group (606) using a plurality of pools (700) having a hierarchical structure (711-715). Each pool (700) represents a different overlapping subset of the issue ports (610). Placing an instruction (600) into a particular pool (700) also reduces vacancies in any one or more subsidiary pools (700) in the hierarchy. In a preferred embodiment, a counter value (702) is associated with each pool (700) to track vacancies. A valid instruction group (606) is formed by picking the placed instructions (600) from the pools (700). The instruction groups are generated accurately and automatically. Decoding errors and stalls are minimised or completely avoided.