| 发明名称 |
Integrated Circuit With Transistor Array And Layout Method Thereof |
| 摘要 |
A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N. The first transistors have the same channel length, and the second transistors have the same channel length. |
| 申请公布号 |
US2016266597(A1) |
申请公布日期 |
2016.09.15 |
| 申请号 |
US201615161585 |
申请日期 |
2016.05.23 |
| 申请人 |
Taiwan Semiconductor Manufacturing CO., LTD. |
发明人 |
Chang Ching-Ho;Horng Jaw-Juinn;Peng Yung-Chow |
| 分类号 |
G05F3/26;H01L27/07;G06F17/50;H01L27/06 |
主分类号 |
G05F3/26 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A current mirror circuit, comprising:
a first current mirror leg configured with N stages of first transistors coupled in series and with their respective gates tied together; and a second current mirror leg configured with N stages of second transistors coupled in series and with their respective gates tied together, wherein the first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N, wherein the first transistors are configured to have the same channel length, and the second transistors are configured to have the same channel length. |
| 地址 |
Hsinchu TW |
