发明名称 Chip embedded substrate and method of producing the same
摘要 An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.
申请公布号 US9451702(B2) 申请公布日期 2016.09.20
申请号 US201414321030 申请日期 2014.07.01
申请人 SHINKO ELECTRIC INDUSTRIES CO., LTD. 发明人 Yamano Takaharu;Iizuka Hajime;Sakaguchi Hideaki;Kobayashi Toshio;Arai Tadashi;Kobayashi Tsuyoshi;Koyama Tetsuya;Iida Kiyoaki;Mashima Tomoaki;Tanaka Koichi;Kunimoto Yuji;Yanagisawa Takashi
分类号 H05K1/18;H01L21/683;H01L23/552;H01L23/00;H01L25/10;H01L25/16;H01L21/56;H01L23/31;H01L23/498;H01L23/538;H05K3/20;H05K3/46 主分类号 H05K1/18
代理机构 Ladas & Parry LLP 代理人 Ladas & Parry LLP
主权项 1. An electronic part embedded substrate comprising: a first substrate; a second substrate provided on the first substrate; an electronic part provided between the first substrate and the second substrate; an electrically connecting member configured to electrically connect the first substrate to the second substrate, wherein the electrically connecting member is provided between the first substrate and the second substrate; and a sealing member configured to completely fill a space between the first substrate and the second substrate to seal the electronic part and the electrically connecting member, wherein the second substrate includes an outermost insulation layer that forms a front surface of the electronic part embedded substrate and an outer connection part embedded in the outermost insulation layer, a front surface of the outer connection part is exposed from a front surface of the outermost insulation layer, a side surface and a back surface of the outer connection part are covered by the outermost insulation layer, a via hole is provided on the back surface of the outer connection part so as to expose the back surface of the outer connection part on the back surface of the outermost insulation layer, a wiring portion is provided on the back surface of the outmost insulation layer so that the wiring portion is connected with the back surface of the outer connection part through the via hole, and the wiring portion is connected with another wiring portion included in the first substrate through the electrically connecting member.
地址 Nagano-shi, Nagano JP