A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.
申请公布号
EP1554647(A1)
申请公布日期
2005.07.20
申请号
EP20030748384
申请日期
2003.09.17
申请人
KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人
ALBA PINTO, CARLOS, A.;SETHURAMAN, RAMANATHAN;SRINIVASAN, BALAKRISHNAN;PETERS, HARM, J., A., M.;PESET LLOPIS, RAFAEL