SiGe surface passivation by germanium cap

摘要

The present disclosure relates to a transistor device having a germanium cap layer that is able to provide for a low interface trap density, while meeting effective oxide thickness scaling requirements, and a related method of fabrication. In some embodiments, the disclosed transistor device has a channel layer disposed within a semiconductor body at a location between a source region and a drain region. A germanium cap layer is disposed onto the channel layer. A gate dielectric layer is separated from the channel layer by the germanium cap layer, and a gate region is disposed above the gate dielectric layer. Separating the gate dielectric layer from the channel layer allows for the germanium cap layer to prevent diffusion of atoms from the channel layer into the gate dielectric layer, thereby provide for a low interface trap density.

主权项

1. A transistor device, comprising:
a layer of semiconductor material overlying a substrate and comprising a source region and a drain region, wherein the source region and the drain region have upper surfaces that are aligned with an upper surface of the layer of semiconductor material; a germanium cap layer vertically overlying the upper surface of the layer of semiconductor material; a gate dielectric layer vertically overlying the germanium cap layer and separated from the layer of semiconductor material by the germanium cap layer, wherein the germanium cap layer is in direct contact with the layer of semiconductor material and the gate dielectric layer; and a gate electrode disposed over the gate dielectric layer and configured to control a flow of charge carriers between the source region and the drain region.