发明名称 COMPILER FOR TRANSLATING BETWEEN A VIRTUAL IMAGE PROCESSOR INSTRUCTION SET ARCHITECTURE (ISA) AND TARGET HARDWARE HAVING A TWO-DIMENSIONAL SHIFT ARRAY STRUCTURE
摘要 A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.
申请公布号 US2016313984(A1) 申请公布日期 2016.10.27
申请号 US201514694856 申请日期 2015.04.23
申请人 Google Inc. 发明人 Meixner Albert
分类号 G06F9/45;G06F9/30 主分类号 G06F9/45
代理机构 代理人
主权项 1. A method, comprising: translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis, the translating comprising replacing some of the higher level instructions having the instruction format with lower level shift instructions that are to shift data within the shift register array structure when executed by respective execution units of the execution lanes, the translating also comprising replacing others of the higher level instructions having the instruction format with lower level memory access instructions that specify a respective external memory address, the lower level memory access instructions to be executed by respective memory units within respective execution lanes of the execution lane array to access respective external memory space that is external to the respective execution lanes that execute the lower level memory access instructions to access the external memory space.
地址 Mountain View CA US