发明名称 |
Semiconductor memory device having an electrically floating body transistor |
摘要 |
An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region. |
申请公布号 |
US9450090(B2) |
申请公布日期 |
2016.09.20 |
申请号 |
US201514930049 |
申请日期 |
2015.11.02 |
申请人 |
Zeno Semiconductor, Inc. |
发明人 |
Widjaja Yuniarto;Or-Bach Zvi |
分类号 |
G11C7/00;H01L29/78;G11C11/404;H01L27/108;H01L29/772;G11C7/22;G11C11/4074;G11C11/4094;G11C11/04 |
主分类号 |
G11C7/00 |
代理机构 |
Venable LLP |
代理人 |
Venable LLP ;Schwarz Steven J.;Ostler Trent B. |
主权项 |
1. An integrated circuit comprising:
an array of memory cells formed in a semiconductor, the array comprising:
a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising:
a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, wherein the second thickness is greater than the first thickness; anda gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region. |
地址 |
San Jose CA US |