| 摘要 |
A circuit for generating at least two rectangular signals with adjustable phase shift, comprises a frequency divider circuit that receives a clock signal as input and provides a signal as output, at least two comparators that receive, respectively, a first threshold voltage and at least a second threshold voltage at one input, and a ramp signal, synchronized with the clock signal, at a second input, the at least two threshold voltages allowing the value of the phase shift between the at least two rectangular signals to be adjusted, and at least two D-type flip-flops that receive, respectively, the output signal from the first comparator and the output signal from the second comparator at their clock inputs, and the output signal from the frequency divider circuit at their D-input. |
