| 摘要 |
Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2, and a pullup resistor is connected between the bus lines and a power source. A state detector detects a frozen state on the basis of the states of the SCL line and SDA line and outputs a freeze detection signal, and it detects a freeze released state so as to output a freeze-release detection signal. A pulse generator supplies a pulse signal corresponding to a clock signal to the SCL line in accordance with the freeze-release detection signal. A reset signal generator sends a reset signal to the multiple master devices in accordance with the freeze-release detection signal. The multiple master devices return to the normal communication state in accordance with the supply of the reset signal. It is possible to restore the system even when the slave device returns an acknowledge signal for an incorrect bit and the IIC bus communication freezes.
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