发明名称 |
REUSE OF DECODED INSTRUCTIONS |
摘要 |
Systems and methods are disclosed for reusing fetched and decoded instructions in block-based processor architectures. In one example of the disclosed technology, a system includes a plurality of block-based processor cores and an instruction scheduler. A respective core is capable of executing one or more instruction blocks of a program. The instruction scheduler can be configured to identify a given instruction block of the program that is resident on a first processor core of the processor cores and is to be executed again. The instruction scheduler can be configured to adjust a mapping of instruction blocks in flight so that the given instruction block is re-executed on the first processor core without re-fetching the given instruction block. |
申请公布号 |
WO2016210022(A1) |
申请公布日期 |
2016.12.29 |
申请号 |
WO2016US38845 |
申请日期 |
2016.06.23 |
申请人 |
MICROSOFT TECHNOLOGY LICENSING, LLC |
发明人 |
BURGER, Douglas Christopher;SMITH, Aaron |
分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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