Apparatus for executing the argument reduction in exponential computations of IEEE standard floating-point numbers.

摘要

An apparatus (57) for executing the argument reduction stage in the computation of F(x)=2**x-1 (with ¦x¦ <1), i.e. determining the value of xi and computing (x-xi) according to the IEEE 754 standard floating-point format comprising: a) a first functional block (59) operative to perform pipeline ADD/SUB/COMPARE operations on a N bits mantissa (e.g. N = 64 mantissa bits + 3 rounding precision bits according to the 80-bit double-extended precision IEEE 754 standard format) including aligner means (44) and a N+1 bits output register (39) whose most significant bit is the carry-out bit generated by the mantissa adder (37); the output of said first functional block is connected to: b) a normalizer means (40') of N+4 bits whose three left-most inputs are tied to "zero" and whose three left-most out bits J(0:2) are output on a three-bits bus (J-BUS); c) a leading zero detector/encoder means (41); said apparatus further comprising: d) a second functional block (60) operative to perform pipeline operations on exponents connected to an encoder means (43) whose output controls said aligner means; e) a selector circuit (61) driven by the outputs of said detector/encoder means (41) and encoder means (43) whose output controls said normalizer means (40'); f) a xi determining circuit (62) that calculates bits K(1) and K(2) from bits J(0:2) such as: K(1) = J(0) OR J(1> K(2) = J(0) OR J(2> and generates the xi mantissa on a xi-BUS connected to said first functional block such as: mantissa xi = 0 K(1) K(2) 1 0 ..... 0; and, g) ROM means (58) to store the F(xi) values whose output is connected to inputs of said first and second functional blocks for the respective mantissa and exponent parts of F(xi). <IMAGE>