| 摘要 |
<p>The present invention provides a source synchronous type interface circuit in which, for fetch of a transmitted data, a source synchronous clock (112) indicating a transmission timing of the data is transmitted from a transmission side (101) to a reception side (102) along with the data, so that a reception clock is generated to define an operation timing of a first reception flip-flop (109) for taking in a data from the reception signal of the source synchronous clock. The interface further includes: a second reception flip-flop (110) for feeding an output from the first reception flip-flop further to a second reception flip-flop in synchronization with a common system clock; and a variable delay circuit (120) for absorbing phase fluctuations of the first reception flip-flop depending on the delay time of transmission, so as to assure a phase difference required for correctly receiving the data. The variable delay circuit has a delay amount automatically controlled according to the phase difference between the system clock and the source synchronous clock received. <IMAGE></p> |
