发明名称 |
Integrated decision feedback equalizer and clock and data recovery |
摘要 |
<p>In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.</p> |
申请公布号 |
EP1545045(A2) |
申请公布日期 |
2005.06.22 |
申请号 |
EP20040028869 |
申请日期 |
2004.12.06 |
申请人 |
BROADCOM CORPORATION |
发明人 |
MOMTAZ, AFSHIN;TONIETTO, DAVIDE |
分类号 |
H03L7/08;H03L7/089;H03L7/091;H04L7/02;H04L7/033;H04L25/03;(IPC1-7):H04L7/033 |
主分类号 |
H03L7/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|