发明名称 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
摘要 |
A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.
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申请公布号 |
US2008067617(A1) |
申请公布日期 |
2008.03.20 |
申请号 |
US20070856481 |
申请日期 |
2007.09.17 |
申请人 |
SANYO SEMICONDUCTOR CO., LTD. |
发明人 |
HACHIYANAGI TOSHIHIRO;UEHARA MASAFUMI;ANZAI KATSUYOSHI |
分类号 |
H01L29/78;H01L21/336 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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