| 摘要 |
A false-trigger free power-rail ESD clamp protection circuit includes an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel. The circuit, in a smaller layout area, has very strong electrostatic charge discharge capability under ESD impact, little power leakage during normal power-up, and relatively strong false-trigger immunity capability for quick power-up. |
| 主权项 |
1. A false-trigger free power-rail ESD clamp protection circuit, wherein the circuit comprises an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel; the ESD impact detection component comprises NMOS transistors (Mcn1) and (Mcn2), a capacitor (C1) and a resistor (R1); the discharge transistor is a NMOS transistor (Mbig); the discharge transistor turn-on channel comprises PMOS transistors (Mp2-1), (Mp2-2) and (Mp3) and an NMOS transistor (Mn2); and the discharge transistor shutoff channel comprises PMOS transistors (Mp4), (Mp5) and (Mp6), NMOS transistors (Man1), (Man2), (Mbn1), (Mbn2), (Mn3), (Mn4-1) and (Mn4-2), and capacitors (C2) and (C3). |
