| 摘要 |
A digital signal processor includes an instruction executer configured to execute instructions. The instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The instruction executer outputs a processed data including the first minimum data and the second minimum data. A bit length of the first minimum data is equal to n bits in length. A bit length of the second minimum data is equal to n bits in length. A bit length of the processed data is equal to at least 2n bits in length.
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