发明名称 |
Memory devices and memory operational methods including single erase operation of conductive bridge memory cells |
摘要 |
Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state. |
申请公布号 |
US9349450(B2) |
申请公布日期 |
2016.05.24 |
申请号 |
US201313914415 |
申请日期 |
2013.06.10 |
申请人 |
Micron Technology, Inc. |
发明人 |
Otsuka Wataru;Kunihiro Takafumi;Tsushima Tomohito;Kitagawa Makoto;Sumino Jun |
分类号 |
G11C13/00;H01L27/10 |
主分类号 |
G11C13/00 |
代理机构 |
Wells St. John P.S. |
代理人 |
Wells St. John P.S. |
主权项 |
1. A memory device comprising:
a plurality of conductive bridge memory cells arranged in an array, the array comprising X banks each comprising Y tiles each comprising Z sub-tiles, wherein each of the Z sub-tiles comprises N of the conductive bridge memory cells and N>1; Z common conductors each associated with one of the Z sub-tiles and the N conductive bridge memory cells of the one of the Z sub-tiles; circuitry located at least partially with the array to write and read a memory state of the conductive bridge memory cells located in a page of the memory cells which are located across a plurality of the Z sub-tiles, wherein the page of the memory cells comprises less than the N conductive bridge memory cells; and wherein the circuitry is configured to erase the N conductive bridge memory cells which are associated with one of the Z common conductors in a single erase operation. |
地址 |
Boise ID US |