发明名称 DELAY CIRCUIT, DELAY CONTROL DEVICE, MEMORY CONTROL DEVICE AND INFORMATION TERMINAL APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To provide a delay circuit that can implement a sufficient delay amount adjustment range by increasing the frequency of updating the amount of delay of delay elements and suppressing control complexity. <P>SOLUTION: A delay circuit 131 includes a first delay section 133 and a second delay section 132 connected in series to generate a delay signal 153 by delaying an input signal. The first delay section 133 has a first signal transmission path, and changes a first delay amount applied to the input signal by switching a signal transmission path for the transmission of the input signal of the first signal transmission path according to a first delay control valve 151. The second delay section 132 has a second signal transmission path, and changes a second delay amount applied to the input signal not by switching the second signal transmission path for the transmission of the input signal but according to a second delay control value 152. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012100058(A) 申请公布日期 2012.05.24
申请号 JP20100245714 申请日期 2010.11.01
申请人 PANASONIC CORP 发明人 MURAKAMI DAISUKE
分类号 H03K5/131;H03K5/14 主分类号 H03K5/131
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