发明名称 |
Methods for gate-length biasing using annotation data |
摘要 |
Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.
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申请公布号 |
US8185865(B2) |
申请公布日期 |
2012.05.22 |
申请号 |
US20100717885 |
申请日期 |
2010.03.04 |
申请人 |
GUPTA PUNEET;KAHNG ANDREW B.;TELA INNOVATIONS, INC. |
发明人 |
GUPTA PUNEET;KAHNG ANDREW B. |
分类号 |
G06F17/50;G06F15/04 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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