TIME TO DIGITAL CONVERTER AND PHASE LOCKED LOOP

摘要

A phase locked loop is disclosed having a frequency controlled oscillator (42), a feedback path, a time to digital converter (10) and a memory. The frequency controlled oscillator (42) comprises a first control input (135, 136) for varying the frequency of the output (106) of the frequency controlled oscillator (42) so as to track a reference frequency (101) and a second control input (139) for modulating the frequency of the output signal (106) so as to produce a chirp. The feedback path is configured to provide an input signal (107) to the time to digital converter (10), and comprises modulation cancelling module (14) operable to remove the frequency modulation resulting from the second control input (139) from the output signal (106). The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input (139). The phase locked loop is operable in a chirp mode, in which the second control input (139) is produced by determining a value for the second control input (139) corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input (135, 136) based on the feedback path from which the modulation cancelling module (14) has removed the frequency modulation resulting from the second control input (139).

主权项

1. A phase locked loop having a frequency controlled oscillator, a feedback path, a time to digital converter, and a memory, wherein:
the frequency controlled oscillator comprises a first control input for varying a frequency of an output signal of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp; the feedback path is configured to provide an input signal based on the output signal of the frequency controlled oscillator to the time to digital converter, and comprises a modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal; the memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in a response of the frequency controlled oscillator to the second control input; and wherein the phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.