| 摘要 |
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. |
| 主权项 |
1. A semiconductor memory device, comprising:
a stack position identifier configured to identify a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices, wherein the plurality of semiconductor devices are coupled together; a phase detector configured to detect a phase of a data strobe relative to an internal data signal, wherein the phase detector includes:
a transition detector configured to provide a pulse signal in response to detection of a transition of the data strobe;a first latch configured to receive the internal data signal, wherein the first latch is configured to be closed in response to the pulse signal; anda second latch configured to receive an output from the first latch and to provide an adjusted data strobe signal, wherein the second latch is configured to be opened in response to the pulse signal; and a phase adjustor configured to delay the internal data signal to substantially match the data strobe. |
