| 摘要 |
<p>There is provided a single wire bus architecture comprising a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a communication protocol implemented over the single wire bus and employed by the master device and the at least one slave device; wherein when one of the at least one slave devices wishes to communicate with the master device, the one of the at least one slave devices discharges the clock signal during a tri-state stage of the clock signal; and wherein the single wire bus transmits a clock signal, power and data between the master device and the one of the at least one slave device in communication with the master device.</p> |
