Memory error generating method, apparatus and computer program product

摘要

In one form of the invention, an apparatus has a first switch operable in an error injection state for interrupting a transfer of first data from a memory device to a test system, and in a normal state for permitting unimpeded data transfer. The apparatus has a second switch operable in an error injection state for sending second data to the test system instead of corresponding bits of the first data. Logic circuitry of the apparatus reads the first data and controls an error injection sequence that includes switching the first and second switches from their respective normal states to their respective error injection states responsive to receiving the command. The apparatus determines whether at least one of the corresponding data bits of the first and second data have disparate logic states independently of switching the first and second switches back to their respective normal states.