发明名称 DEVICE AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To shorten a testing time and enhance throughput. SOLUTION: This semiconductor integrated circuit tester for testing a plurality of devices to be tested applying a test pattern to them, is equipped with judgment means for performing pass/fail judgment of output data output from pins of the plurality of devices to be tested according to a test pattern applied to the pins, by comparing the output data with a predetermined expected value, judgment result memory means for individually memorizing a pass/fail judgment result by the judgment means in correspondence with a pin of each device to be tested, and judgment result writing control means for directing the judgment result memory means to memorize a pass/fail determination result corresponding to a pin of each device to be tested, when at least one of the output data is judged to be a "fail" in the judgment means. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007322141(A) 申请公布日期 2007.12.13
申请号 JP20060149509 申请日期 2006.05.30
申请人 YOKOGAWA ELECTRIC CORP 发明人 SHIMIZU AKIRA
分类号 G01R31/28;G11C29/44 主分类号 G01R31/28
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