TIME DIVISION MULTIPLEXED MULTIPORT MEMORY

摘要

In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.

主权项

1. A circuit, comprising:
a single-port (SP) memory; a time division multiplexing (TDM) circuit configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal; an input port selector configured to select current input data before a first time within one of the at least one pulse, and select next input data starting from the first time to generate selected data; an first input port storage element configured to receive the selected data from the input port selector and provide data passed through or stored in the first input port storage element, wherein the provided data is the current input data substantially throughout the one of the at least one pulse; and
the SP memory is configured to be accessed based on the provided data by the first input port storage element in response to the internal clock signal.