| 摘要 |
Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications. |
| 主权项 |
1. A semiconductor device structure comprising:
a GaN power switching device comprising a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die); the GaN die comprising an on-chip metallization layer defining source, drain and gate contact areas on a front-side of the GaN die, said source and drain contact areas being distributed over an active area of the lateral GaN power transistor and providing a first level of interconnect to a plurality of underlying source and drain electrodes of the lateral GaN power transistor; an overlying second level of interconnect comprising a dielectric layer formed on the GaN die defining contact openings to the underlying source, drain and gate contact areas of the on-chip metallization layer and a second metallization layer formed thereon defining a source contact area, a drain contact area and one or more gate contact areas, the thickness and lateral dimensions of the source contact area and drain contact area of the second metallization layer being greater than those of the underlying source and drain contact areas of the on-chip metallization layer; and packaging components comprising one or more dielectric layers forming a dielectric body of a package and package metallization; the GaN chip and overlying second level of interconnect being embedded in the dielectric body of the package with the dielectric body of the package extending laterally around the GaN die; the package metallization comprising: an overlying metal layer and an underlying metal layer sandwiching the dielectric body of the package, the overlying metal layer extending over a front-side of the dielectric body and the underlying metal layer extending over a back-side of the dielectric body, the overlying metal layer being patterned to define large area source and drain contact areas extending laterally of the underlying GaN die, and one or more gate contact areas; the underlying metal layer being patterned to define a thermal pad underlying a back-side of the GaN die, and an external source contact pad, an external drain contact pad, an external gate contact pad, an external source sense pad, each laterally spaced from the thermal pad; the respective source, drain and gate areas of the second metallization layer on the GaN die being electrically interconnected vertically through the dielectric body of the package with the corresponding source, drain and gate contact areas of the overlying metal layer of the package metallization; the respective source, drain and gate areas of the overlying metal layer being electrically interconnected vertically through the dielectric body of the package with corresponding external source, drain, and gate contact pads of the underlying metal layer of the package metallization; and the back-side of the GaN die being thermally coupled to the thermal pad. |
