Scalable decode-time instruction sequence optimization of dependent instructions

摘要

Producer-consumer instructions, comprising a first instruction and a second instruction in program order, are fetched requiring in-order execution, the second instruction is modified by the processor so that the first instruction and second instruction can be completed out-of-order, the modification comprising any one of extending an immediate field of the second instruction using immediate field information of the first instruction or providing a source location of the first instruction as an additional source location to source locations of the second instruction.

主权项

1. A computer system for executing dependent machine instructions of an instruction set architecture (ISA) out-of-order, the system comprising:
a processor configured to communicate with a main storage, the processor comprising an instruction fetcher, an instruction modifier and one or more execution units, the processor configured to perform a method comprising: fetching for execution, by the processor, a first instruction of the ISA and a second instruction of the ISA; determining out-of-order execution candidacy, by the processor, of the first instruction and the second instruction, wherein the first instruction and second instruction are configured to be executed in-order but are candidates for modification of the second instruction to create a new second instruction to permit its execution out-of-order, the determination comprising determining that the first instruction specifies a target operand location for a target operand and the second instruction specifies a source operand location for a source operand, wherein the first instruction is configured to store a target operand at the target operand location, wherein the source operand location is the same as the target operand location, wherein the second instruction is configured to obtain the source operand at the source operand location; and based on the determining out-of-order execution candidacy, executing, by the processor, the first instruction and the second instruction by executing, by the processor, the first instruction of the ISA and a new second instruction not of the ISA, wherein the new second instruction is not dependent on the target operand of the first instruction.