NON-UNIFORM GATE DIELECTRIC FOR U-SHAPE MOSFET

摘要

A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.

主权项

1. A semiconductor structure comprising:
a functional gate structure located on a semiconductor material portion, wherein said functional gate structure comprises a U-shaped gate dielectric structure and a gate conductor portion, said U-shaped gate dielectric structure comprises a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from and surrounding exposed sidewalls of said horizontal gate dielectric portion, said vertical gate dielectric wall portion has a lateral thickness that is greater than said vertical thickness of said horizontal gate dielectric portion, and said gate conductor portion is located on said horizontal gate dielectric portion and within an area confined by said vertical gate dielectric wall portion; and a source region located on one side of said functional gate structure and a drain region located on another side of the functional gate structure, wherein a source-side semiconductor material is positioned between said source region and a portion of said semiconductor material portion, and a drain-side semiconductor material is positioned between said drain region and another portion of said semiconductor material portion, said source region and said drain region each have a topmost surface that is located above a topmost surface of said semiconductor material portion and a topmost surface of said horizontal gate dielectric portion, and wherein each of said horizontal gate dielectric portion and said vertical gate dielectric wall portion has a bottommost surface that is coplanar with a bottommost surface of each of said source-side semiconductor material and said drain-side semiconductor material.