| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing a reduction in potential of a bit line precharged by the off-leakage of a transfer gate transistor during data reading from an SRAM cell and performing high-speed reading. SOLUTION: This semiconductor memory device supplies write data through first and second bit lines to a cell array having a plurality of SRAM cells SC11 to SCm1 connected between the first and second bit lines BL1 and BL2 through first and second data storage nodes, a plurality of word lines WL1 to WLm arrayed in a second direction intersecting the bit lines, and SRAM cells selected by the word lines on a write mode. The semiconductor memory device is provided with data write circuits W1 to Wn for writing back read data read from the SRAM cell selected by the word line to the first bit line on a reading mode to the first bit line. COPYRIGHT: (C)2005,JPO&NCIPI
|
