发明名称 SYSTEM AND METHOD FOR PLL CONTROL
摘要 <P>PROBLEM TO BE SOLVED: To provide a system and a method for reducing influences of logic operation on a phase-locked loop (PLL) circuit. <P>SOLUTION: The system and method may permit a PLL circuit to compensate for the anticipated influences of an instruction before, simultaneously with, or after the execution of the instruction. More particularly, logic related to the issue of instructions in a system may provide a signal to a PLL in the system based on an instruction. After that, the PLL may be adjusted to compensate for the anticipated influences of the instruction based on this control signal. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006345511(A) 申请公布日期 2006.12.21
申请号 JP20060145794 申请日期 2006.05.25
申请人 TOSHIBA CORP 发明人 TAKASE SATORU
分类号 H03L7/06;H03L7/14 主分类号 H03L7/06
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