发明名称 Method for reducing silicide spiking in a gate
摘要 A first silicon oxide layer and a polysilicon layer are formed on a silicon substrate of a semiconductor wafer, followed by a rapid thermal oxidation (RTO) process to form a second silicon oxide layer on the polysilicon layer. The second silicon oxide layer is subsequently removed. A barrier layer and a silicide layer are formed on the polysilicon layer, and a lithographic process and an etching process are performed to form a gate. Finally, a thermal process is performed to allow metal ions, that diffuse from both the silicide layer and the barrier layer to the interface of the polysilicon layer and the barrier layer, to react with the oxygen atoms absorbed by the polysilicon layer during the RTO process, to form a metallic oxide layer so as to reduce silicide layer spiking.
申请公布号 US2002168591(A1) 申请公布日期 2002.11.14
申请号 US20010851578 申请日期 2001.05.10
申请人 LEE CHIU-TE 发明人 LEE CHIU-TE
分类号 G03F7/00;G03F7/40;H01L21/28;H01L29/49;(IPC1-7):G03F7/00 主分类号 G03F7/00
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