Semiconductor memory having a delay locked loop

摘要

A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output drivers with an externally supplied clock signal. An updating of the delay locked loop is suppressed during a Read state of the semiconductor memory. An appropriate control signal is produced by a state machine and is supplied to the delay locked loop. The synchronization of the data output with the supplied clock signal can be achieved in a precise manner and requires only simple circuitry.