发明名称 SYSTOLIC ARRAY
摘要 PROBLEM TO BE SOLVED: To provide a one-dimensional MFA (modified Faddeeva algorithm) systolic array which reduces the memory for storing input/output data by making a matrix size of computation variable to equalize the load. SOLUTION: In the systolic array for matrix computation using an MFA, downward square MFA array processing and upward square MFA array processing are mapped to a one-dimensional array in horizontal directions, and downward and upward MFA matrix computations for two threads are executed in each PE in the one-dimensional array, and an input and an output are provided for each of PEs at both ends of the one-dimensional array. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008027234(A) 申请公布日期 2008.02.07
申请号 JP20060199682 申请日期 2006.07.21
申请人 NEC ELECTRONICS CORP 发明人 SEKI KATSUTOSHI
分类号 G06F17/16 主分类号 G06F17/16
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