| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an image processing circuit without interruption of image processing. <P>SOLUTION: Each unit among a plurality of image processing units having a pipeline structure receives an updated configuration vector, and the configuration vector is only applied in synchronization with a timing-derived trigger signal within a time period. A hardware-enable signal is logically combined with a timing-derived triggering event signal to control a switch that applies the received new configuration vector to the image processing unit. This ensures that each image processing unit (stage) in a chain type of image processing units is updated in sequence even if a CPU outputs the updated configuration vector independently of timing of data and without regard to a delay of each image processing unit. <P>COPYRIGHT: (C)2012,JPO&INPIT |
