发明名称 |
SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF |
摘要 |
PROBLEM TO BE SOLVED: To obtain a desired work function by especially suppressing a reaction between a high dielectric constant material and a gate electrode material, which causes a fermi level pinning phenomenon, and to increase uniformity and yield in a CMOS transistor structure employing a full silicide gate or a metal gate. SOLUTION: A CMOS semiconductor apparatus is provided with an n-type transistor having a gate insulation film 104A consisting of an HfSiON and a gate electrode 106B wholly consisting of a nickel silicide, and a p-type transistor having a gate insulation film 104A consisting of an HfSiON and a gate electrode 106D wholly consisting of a nickel silicide, both electrodes being successively formed on a substrate 101 made of Si. The metal concentration of a p-side gate electrode 106C is set higher than the metal concentration of the n-side gate electrode 106B. COPYRIGHT: (C)2007,JPO&INPIT
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申请公布号 |
JP2006344836(A) |
申请公布日期 |
2006.12.21 |
申请号 |
JP20050170208 |
申请日期 |
2005.06.09 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD;INTERUNIVERSITAIR MICRO ELECTRONICA CENTRUM VZW |
发明人 |
HAYASHI SHIGENORI;MIHASHI RIICHIRO |
分类号 |
H01L27/092;H01L21/28;H01L21/8238;H01L29/423;H01L29/49 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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