| 摘要 |
PROBLEM TO BE SOLVED: To eliminate difference in level between the upper part of a capacitor and the upper part of a wiring on the surface of a transistor array panel. SOLUTION: A signal line group Y is patterned and a gate 21g of a transistor 21 and an electrode 24a of the capacitor 24 are patterned and then a gate insulating film 31 is formed. A semiconductor film 81 is formed on the gate insulating film 31, a channel protection film 21p is patterned and an insulating film 72 is patterned in such a manner so as to overlap the signal line group Y. Ohmic films 21a and 21b are patterned, and a semiconductor film 71 and a semiconductor film 21c are obtained from a semiconductor film 81 by etching. A scanning line X and a supply line Z are patterned, and a source 21s and a drain 21d of the transistor 21, and an electrode 24b of the capacitor 24 are patterned. A protection insulating film 32 is formed, a planarization film 33 is formed, and an organic EL element L is patterned for every pixel. COPYRIGHT: (C)2007,JPO&INPIT
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