ENHANCED PRIORITISING AND UNIFYING INTERRUPT CONTROLLER

摘要

An enhanced interrupt controller is provided which is able to receive both hardware-generated and software-generated request signals. Data associated with each received interrupt or request signal is stored in a storage unit within the enhanced interrupt controller in an order which depends on the priority level of the data and, for data of the same level of priority, on the chronological order of receipt. The enhanced interrupt controller instructs the processor, with which it is in communication, to read the stored data from the controller in the stored order ensuring that data of higher priority is read before data of lower priority. A method of routing hardware-generated and software-generated signals from an enhanced interrupt controller to a processor is also disclosed.