ESTIMATING CACHE SIZE FOR CACHE ROUTERS IN INFORMATION CENTRIC NETWORKS

摘要

A technique for estimating cache size for cache routers in information centric networks (ICNs) is disclosed. In an example, an average rate of incoming requests and a probability of occurrence of each request at a cache router in a predefined time interval is determined. Further, a relation between cache hit and cache miss with and without replacement is derived based on the probability of occurrence of each request. Furthermore, an entropy of the requests is computed based on the probability of occurrence of each request. Moreover, a diversity index of the requests is calculated based on the entropy and the average rate of the requests. A cache size for the cache router is then estimated based on a user defined probability of cache hit, the average rate of the requests, the diversity index of the requests and the relation between the cache hit and cache miss with and without replacement.

主权项

1. A processor-implemented method comprising:
determining, by one or more hardware processors, an average rate of incoming requests and a probability of occurrence of each of the incoming requests at a cache router in a predefined time interval; deriving, by the one or more hardware processors, a relation between a cache hit, cache miss with replacement and cache miss without replacement in the predefined time interval based on the probability of occurrence of each of the incoming requests; computing, by the one or more hardware processors, an entropy of the requests based on the probability of occurrence of each of the requests in the predefined time interval; calculating, by the one or more hardware processors, a diversity index of the requests based on the entropy of the requests and the average rate of the requests; and estimating, by the one or more hardware processors, a cache size for the cache router based on a user defined probability of cache hit, the average rate of the requests, the diversity index and the relation between the cache hit, cache miss with replacement and cache miss without replacement.