发明名称 CLOCK GENERATION CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a clock generation circuit which generates a clock for the portion of shortage internally and automatically in a picture processor carrying out pipeline processing etc. <P>SOLUTION: The clock generation circuit is used for generating an additional clock signal to an input clock signal. In one method, a delay circuit delays the input clock signal by a delay time corresponding to the number of required clocks to generate a delayed clock signal, and the input clock signal and the delayed clock signal are outputted to increase the number of clocks. In another method, additional clock pulse generation part is provided by the number of stages according to the number of required clocks to generate additional clock pulses. In another method in addition, when a clock pulse becomes absent in the input clock signal, a counter counts a period corresponding to the number of required additional clocks, and the internal clock signal is outputted as the additional clocks through the period. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2006270503(A) 申请公布日期 2006.10.05
申请号 JP20050085563 申请日期 2005.03.24
申请人 SANYO EPSON IMAGING DEVICES CORP 发明人 KURUMISAWA TAKASHI
分类号 G06F1/06;G06T1/20;H03K5/14 主分类号 G06F1/06
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