发明名称 TUNABLE DUPLEXING CIRCUIT
摘要 A tunable duplexer circuit is described, wherein the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. A method is described where the duplexer circuit characteristics are optimized in conjunction with a specific antenna frequency response to provide additional out-of-band rejection in a communication system. Dynamic optimization of both the duplexer circuit and an active antenna system is described to provide improved out-of-band rejection when implemented in RF front-end circuits of communication systems. Other features and embodiments are described in the following detailed descriptions.
申请公布号 US2016294350(A1) 申请公布日期 2016.10.06
申请号 US201615182412 申请日期 2016.06.14
申请人 Ethertronics, Inc. 发明人 Desclos Laurent
分类号 H03H7/01;H03H7/18;H03J3/20;H03H7/46 主分类号 H03H7/01
代理机构 代理人
主权项 1. A tunable band-pass circuit comprising: a first tuning section comprising: a first inductor in series with a first tunable capacitor, the first tunable capacitor being further connected to ground; a second tuning section comprising: a second inductor, a first phase shifter, and a second tunable capacitor in a series configuration, with the second tunable capacitor being further connected to ground;a third inductor connected in parallel across the second inductor and first phase shifter;a first fixed capacitor positioned between the second inductor and the third inductor; and a third tuning section comprising a fourth inductor and a second fixed capacitor in a series configuration forming a first series LC circuit;a fifth inductor and a third fixed capacitor in a series configuration forming a second series LC circuit;a sixth inductor in series with a third tunable capacitor forming a third series LC circuit, a first terminal end of the third series LC circuit connected to a common junction of the first and second series LC circuits, and a second terminal end of the third series LC circuit being connected to ground;a fourth fixed capacitor positioned between the first series LC circuit and the second series LC circuit; the first, second, and third tuning sections being connected in series between a first port and a second port to form a band-pass frequency response; wherein each of the first through third tunable capacitors is configured for variable tuning for changing the frequency response of the circuit.
地址 San Diego CA US