Semiconductor memory apparatus, and impedance calibration circuit and method thereof

摘要

A semiconductor memory apparatus may include a memory cell array. The semiconductor memory apparatus may include an impedance calibration circuit configured to perform an impedance matching operation by generating an impedance code based on a voltage of an interface node determined by an external reference resistor or an internal reference resistor unit according to whether or not to the external reference resistor is coupled to the impedance calibration circuit. The semiconductor memory apparatus may include a data input/output (I/O) driver configured to receive input data from the memory cell array and generate output data in response to the impedance code.

主权项

1. A semiconductor memory apparatus comprising:
a memory cell array; an internal reference resistor unit configured to couple to the an interface node; an impedance calibration circuit configured to perform an impedance matching operation by generating an impedance code based on a voltage of the interface node determined by an external reference resistor or the internal reference resistor unit according to whether or not the external reference resistor is coupled to the impedance calibration circuit; and a data input/output (I/O) driver configured to receive input data from the memory cell array and generate output data in response to the impedance code.